1. Field of the Invention
The present invention relates to a semiconductor storage device and a semiconductor integrated circuit each having a vertical transistor.
2. Related Art
It is concerned that as a DRAM cell constructed by a conventional one transistor and one capacitor having a trench capacitor or a stacked capacitor is becoming smaller, it becomes difficult to fabricate the DRAM cell. As a memory cell which can replace the DRAM cell of this kind, a new memory cell, an FBC, for storing information by accumulating majority carriers in a floating body of an FET formed on a silicon on insulator (SOI) or the like has been proposed (refer to Japanese Patent Application Laid-Open Nos. 2003-68877 and 2002-246571).
As a technique of forming an FBC on a normal bulk silicon wafer without using an SOI wafer, a technique using a transistor (SGT) in which a silicon pillar is surrounded by a gate has been proposed. In the FBC of this kind, the height direction of the silicon pillar corresponds to length L of a channel. Even when the cell is formed finer, the length L can be made longer than that of a plane transistor. There is consequently an advantage such that a relatively thick gate insulating film can be used. In addition, a relatively high body impurity concentration can be set, so that the technique also has advantages such as an increased signal amount and longer data holding time.
The conventional FBC, however, has a drawback such that operation tends to become unstable due to high parasite resistance of a source, and the FBC is subjected to disturbance of “1” by a parasitic bipolar device.
The phenomenon that “operation becomes unstable due to parasitic resistance” is described as follows. At the time of writing “1”, a transistor is operated in a pentode region. For example, when a word line is operated with 1.5V and a bit line is operated also with 1.5V, Vgs of 1.5V and Vds of 1.5V are applied. Under such conditions, a drain current Ids of about 15 μA flows. Therefore, when a source resistance is about 10 KΩ or higher, a voltage drop of about 150 mV or larger occurs. Although the user intends to apply Vds of 1.5V, substantially, about 1.35V or less is applied on the FBC transistor. A hole generation current due to impact ionization decreases and the speed of writing “1” deteriorates very much.
On the other hand, at the time of writing “0”, when a word line is operated with 1.5V and a bit line is operated with −1.5V, Vgs of 3V and Vds of 1.5V are applied. Under the conditions, the drain current of about 50 μA flows. Therefore, when resistance of a source is about 10 KΩ or higher, a voltage drop of about 500 mV or higher occurs. Even when the voltage of the bit line is decreased to −1.5V, about −1V or higher is applied to the FBC transistor. Therefore, since the level of writing “0” is too high, only insufficient data “0” can be written.
FIG. 22 is a cross section view of a conventional semiconductor storage device having an FBC which is consisted of a vertical transistor. An FBC 70 in FIG. 22 has an N-type diffusion layer 73 disposed via a source face 72 on a silicon wafer 71, a silicon pillar 74 formed on the top face of the N-type diffusion layer 73, and an N-type diffusion layer 75 formed on the top face of the silicon pillar 74.
Cells A and B in FIG. 22 share a bit line 76 made of a metal material. On the right and left sides of the silicon pillar 74 of the FBC 70, gates made of polysilicon are formed. One of the gates is connected to a word line 77 and the other gate is connected to a plate line 78.
Since the plate line 78 is set to a minus potential and the silicon pillar 74 of the FBC 70 is formed of a P-type diffusion layer, the interface between the plate line 78 and the silicon pillar 74 is in a hole accumulation state and a predetermined capacity is assured.
It is assumed here that, in the initial state, both of cells A and B are in a “0” state, that is, in a state where the number of holes is small. A situation of writing data “1” into the cell A in this state will be considered. In the situation, the voltage of the word line 77 belonging to the cell A (left word line 77) is increased to 1.5V and the voltage of the bit line is also increased to 1.5V.
In such a state, the cell A operates in the pentode region, electron-hole pairs are generated from a pinch-off point near the drain, and the holes start to be accumulated in the body. Accordingly, the body potential starts rising. When the body potential is raised to a turn-on voltage Vf of a PN junction, as shown in FIG. 23, a current in the PN junction increases, and a part of the holes generated in the body flow out toward the N-type diffusion layer 73 of the source.
Although the ratio of the holes which flow to the N-type diffusion layer 73, re-combine with the electrons and disappear is high, there is probability that a part of the holes is not recombined but is diffused into the diffusion layer 72, passes under the adjacent cell B, and enters the body of the cell B of low potential. It means that, in such a situation, the cell B in which data of “0” is originally written (specifically, a storage state as a state where the number of holes in the body of the cell B is small is held) changes to the state of “1”.
Therefore, when an event of continuously writing “1” into the cell A for a long time, or an event of writing “1” a number of times though each writing period is short occurs, an inconvenience such that the cell B is changed to “1” arises. This inconvenience is disturbance of “1”. In other words, when “1” is written into a cell by the operation of a parasitic PNP bipolar in which the body of the cell A is an emitter, the body of the cell B is a collector, and the diffusion layer 72 between the cells A and B serves as a base, an inconvenience such that a neighboring “0” cell is changed to a “1” cell occurs.